1. Field of the Invention
The present invention is generally related to semiconductor processing, and, more particularly, to process control of alignment in dual damascene processes.
2. Description of the Related Art
A conventional integrated circuit device, such as a microprocessor, is typically comprised of many thousands of semiconductor devices, e.g., transistors, formed above the surface of a semiconducting substrate. For the integrated circuit device to function, the transistors must be electrically connected to one another through conductive interconnections. Many modem integrated circuit devices are very densely packed, i.e., there is very little space between the transistors formed above the substrate. Thus, these conductive interconnections must be made in multiple layers to conserve plot space on the semiconducting substrate. This is typically accomplished through the formation of a plurality of conductive lines and conductive plugs formed in alternative layers of dielectric materials formed on the device. As is readily apparent to those skilled in the art, the conductive plugs are means by which various layers of conductive lines, and/or semiconductor devices, may be electrically coupled to one another. The conductive lines and plugs may be made of a variety of conductive materials, such as copper, aluminum, aluminum alloys, titanium, tantalum, titanium nitride, tantalum nitride, tungsten, etc.
One particular technique used to form such conductive lines and plugs is known as a dual damascene technique. One variation of this technique involves the formation of a first layer of a dielectric material, formation of a relatively thin etch stop layer (for example comprised of silicon nitride) above the first dielectric layer, patterning of the etch stop layer to define openings corresponding to plugs to be formed in the first dielectric layer, and formation of a second dielectric layer above the etch stop layer. Thereafter, an etching process is used to define an opening in the second dielectric layer, and to remove portions of the first dielectric layer positioned under the openings previously formed in the etch stop layer. The openings in the first and second layers of dielectric material correspond to a yet to be formed metal plug and metal line, respectively. Thereafter, the openings in the first and second dielectric layers are filled with an appropriate metal or layers of metal.
The dual damascene technique is very labor-intensive in that it requires the formation of three process layers, the first and second dielectric layers as well as the etch stop layer. In a typical dual-damascene copper process flow, as shown in FIGS. 1A-1E, a first dielectric layer 100 is deposited on a second dielectric layer 105 on a wafer 107. The second dielectric layer 105 has a xe2x80x9chard maskxe2x80x9d (typically silicon nitride, SiN) 110 deposited and patterned thereon, between the first dielectric layer 100 and the second dielectric layer 105. If necessary, the first dielectric layer 100 is planarized using CMP. Metallization patterns are then applied using the hard mask 110 and a patterned photomask 115 (FIG. 1A) and photolithography. Openings (such as trenches 120 and 125) for conductive metal lines, contact holes, via holes, and the like, are etched into both the first dielectric layer 100 and the second dielectric layer 105. The patterned photomask 115 is then stripped (FIG. 1B) and a thin barrier metal layer of tantalum 130A and a copper seed layer 130B are then applied to the entire surface using vapor-phase deposition. The barrier metal layer of tantalum 130A and the copper seed layer 130B blanket-deposit the entire upper surface 135 of the first dielectric layer 100 as well as the side and bottom surfaces of the trenches 120 and 125, forming a conductive surface 140, as shown in FIG. 1C.
The bulk of the copper trench-fill is again done using an electroplating technique, where the conductive surface 140 is mechanically clamped to an electrode to establish an electrical contact, and the wafer 107 is then immersed in an electrolyte solution containing copper ions. An electrical current is then passed through the wafer-electrolyte system to cause reduction and deposition of copper on the conductive surface 140.
This process typically produces a conformal coating 145 of constant thickness across the entire conductive surface 140, as shown in FIG. 1D. Once a sufficiently thick layer of copper 145 has been deposited, the surface of the wafer is planarized using CMP techniques. Ideally, this clears all copper and tantalum barrier metal from the entire upper surface 135 of the first dielectric layer 100, leaving copper only in the copper-filled trenches (such as copper-filled trenches 150 and 155), as shown in FIG. 1E.
The dual-damascene copper process flow, as shown in FIGS. 1A-1E, combines the intermetal via connection formation with the copper trench-fill deposition by etching a more complex pattern before the barrier metal layer and copper seed layer depositions and before the copper trench-fill. The trench etching continues until the via hole (such as trench 125 in FIG. 1B) has been etched out. The dual-damascene copper process flow, as compared to other processes such as the signal-damascene process, significantly reduces the number of processing steps and is typically a preferred method of achieving copper metallization.
Typically, in dual-damascene processes, at least two alignment registrations processes define an alignment from one process layer to the next process layer. In contrast, in single-damascene processes, one alignment registration process can define an alignment from one process layer to another. Alignment misregistration in dual-damascene processes can cause significant reduction in the quality of the processed semiconductor devices.
The present invention is directed to a method and device for solving some or all of the aforementioned problems.
In one aspect of the present invention, a method is provided for performing alignment during processing of a semiconductor device. The method is comprised of: performing alignment registration on a plurality of layers on said semiconductor device; measuring misregistration of said alignment registration in relation to a predetermined standard alignment key; and generating an offset for a subsequent process layer on said semiconductor using said measure misregistration.
In one aspect of the present invention, an apparatus is provided for performing alignment during processing of a semiconductor device. The apparatus of the present invention comprises: means for performing alignment registration on a plurality of layers on said semiconductor device; means for measuring misregistration of said alignment registration in relation to a predetermined standard alignment key; and means for generating an offset for a subsequent process layer on said semiconductor using said measure misregistration.